The continued progressing miniaturization of electronic devices requires an increasingly more compact peripheral integration. Short vertical connections represent an efficient path of electrical contacting. In addition, it is necessary for physical reasons—in order to increase the gain and the maximum output performance of high-performance transistors available per chip—to establish a low-induction electrically conductive connection between the source contacts on the front side and the ground electrode on the rear side. However, considering the technology, this is not always easy to implement.
At the present time, electrically active GaN material (gallium nitride) is virtually not available as a monocrystalline wafer material and is therefore epitactically grown on substrate materials, such as, for example, SiC wafers (silicon carbide). SiC is distinguished by very good thermal conductivity, as well as by an extremely high chemical stability and by great hardness. In order to achieve rear-side contacting of GaN transistors, it is thus necessary to drill through the SiC carrier material, as well as through the superimposed GaN epitaxial layer. Until now, virtually only dry-chemistry etching processes could be used for texturing, such as reactive ion etching in high-performance plasma etching reactors that are specifically optimized for this purpose. Typical plasma etching rates of SiC, however, are 1 μm/min and thus very low. In addition, the use of plasma etching technology requires the fabrication and lithographic texturing of a durable etching mask.
It has been known that vias can be produced in printed circuit boards with the use of lasers. Considering these technologies, the laser is used to drill openings into the copper and dielectric layers, said layers then being metallized in order to produce connections between specific layers. The different laser technologies use CO2 lasers, frequency-doubled (green) YAG lasers, excimer lasers and UV:YAG lasers.
The production of these vias has been described in the following, for example:    L. W. Burgess: “Introducing Via-in-Pad Blind Via Technology to Any PCB Multilayer Fabricator.” IPC Printed Circuits Expo 1997, Mar. 9-13, 1997, San Jose, Calif., S15-2.    A. Cable: “Improvements in High Speed Laser Microvia Formation Using Solid State Nd:YAG UV Lasers.” IPC Printed Circuits Expo 1997, Mar. 9-13, 1997, San Jose, Calif., S17-7.    M. D. Owen: “Via drilling.” In: J. F. Ready, D. F. Farson (Edtrs.): LIA Handbook of laser materials processing, Laser Institute of America, Magnolia Publishing (2001) 661-665.
Methods for the production of vias in substrates have also been known from documents EP 0 926 723 A and U.S. Pat. No. 4,964,212. In these cases, blind holes are drilled into the substrate from the rear side of the wafer. The semiconductor substrate that is named is silicon. Referring to document U.S. Pat. No. 4,964,212 A, a Q-switched Nd:YAG laser (wavelength, 1.06 μm) is used, and reference is made to U.S. Pat. No. 4,437,109 where the use of a frequency-doubled Nd:YAG laser (wavelength, 0,53 μm) is mentioned. An (isolator) layer is applied to the front side of the waver, said layer acting as a laser etching stop, because said layer does not absorb laser radiation. In this case, a metal layer of a contact that absorbs laser radiation would be out of the question.
In accordance with document EP 0 926 723 A a protective layer of metal (Cr) is applied to the rear side, said layer reflecting the laser radiation. Laser machining occurs after the chromium layer has been opened at the machining sites, so that the substrate may be ablated by the laser radiation. To do so, lithographic texturing of the rear side is required. The isolator layer must not deposit on the bottom of the hole, or the layer must later again be removed from the front side (otherwise no electrical contact with the front side would be produced during the subsequent metallization). Consequently, the method is very complicated and uneconomical.
Document US 2005/104 228 A1 deals with methods of packaging micro-electronic devices and with the production of vias and conductive connections in microchips. The fabrication of vertically conductive connections through a chip with an integrated circuit (wafer-level packaging) is described for the use in multi-chip stacks. The surface of the chip is provided with a “redistribution layer” (RDL) of conducting paths that are connected at one end to the bond pad and lead laterally away from there (to solder spheres). The objective is to electrically connect stacked chips to each other. Following the fabrication of the conducting paths, an opening is produced on and in the bond pad, i.e., the metal is completely removed by etching. Later, a hole is produced from the rear side at the same site by the laser. The laser is adjusted relative to the bond pad with the aid of pattern recognition; then said laser drills through the chip at the created opening in the metal, i.e., the bond pad metal is not drilled through. Passivation layers protect the front and rear sides during the laser process and during the subsequent cleaning done by etching. The production of the vertical electrical connection consists of numerous method steps (deposition of TiCL4, TiN, reverse etching, currentless Ni deposition after surface activation by immersion in HF:Pd, metal filling with solder or by electroplating), these making the overall process relatively complex.
Consequently, until now, no effective method based on laser technology has been available for the fabrication of micro-vias in semiconductor wafers.